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ltc3542 1 3542f 500ma, 2.25mhz synchronous step-down dc/dc converter the ltc ? 3542 is a high ef? ciency monolithic synchronous buck converter using a constant frequency, current mode architecture. supply current during operation is only 26a, dropping to <1a in shutdown. the 2.5v to 5.5v input voltage range makes the ltc3542 ideally suited for single li-ion battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. the output voltage is adjustable from 0.6v to v in . internal power switches are optimized to provide high ef? ciency and eliminate the need for an external schottky diode. switching frequency is internally set at 2.25mhz, allowing the use of small surface mount inductors and capacitors, and it can synchronize to an external clock signal with a frequency range of 1mhz to 3mhz through the mode/ sync pin. the ltc3542 is speci? cally designed to work well with ceramic output capacitors, achieving very low output voltage ripple and a small pcb footprint. the ltc3542 can be con? gured for the power saving burst mode ? operation. for reduced noise and rf interference, the mode/sync pin can be con? gured for pulse skipping operation. cellular telephones wireless and dsl modems digital cameras mp3 players pdas and other handheld devices high ef? ciency: up to 96% high peak switch current: 1000ma low output ripple (<20mv p-p typical) burst mode operation: only 26a very low quiescent current: only 26a 2.5v to 5.5v input voltage range 2.25mhz constant frequency operation 1mhz to 3mhz external frequency synchronization low dropout operation: 100% duty cycle no schottky diode required internal soft-start limits inrush current 0.6v reference allows low output voltages shutdown mode draws <1a supply current 2% output voltage accuracy current mode operation for excellent line and load transient response overtemperature protected available in 6-lead 2mm 2mm dfn and small tsot applicatio s u features descriptio u typical applicatio u , ltc, lt and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 5994885. v in ltc3542 run 75k 3542 ta01a 150k 22pf 2.2 h c in 10 f cer c out 10 f cer sw v in 2.7v to 5.5v v out 1.8v 500ma v fb mode/sync gnd ef? ciency and power loss vs output current output current (ma) 30 efficiency (%) power loss (mw) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3542 ta01b 0 100 1000 10 1 0.1 1 v in = 3.6v v out = 1.8v
ltc3542 2 3542f input supply voltage (v in ) ........................... C0.3v to 6v v fb , run voltages .......................................C0.3v to v in mode voltage ................................C0.3v to (v in + 0.3v) sw voltage ....................................C0.3v to (v in + 0.3v) operating ambient temperature range (note 2) .................................................... C40c to 85c (note 1) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.6v unless otherwise noted. symbol parameter conditions min typ max units v in operating voltage range 2.5 5.5 v i fb feedback input current 30 na v fb feedback voltage (note 4) 0.588 0.6 0.612 v v line_reg reference voltage line regulation (note 4) v in = 2.5v to 5.5v 0.04 0.2 %/v v load_reg output voltage load regulation (note 4) i load = 100ma to 500ma 0.02 0.2 % i s input dc supply current (note 5) active mode sleep mode shutdown v fb = 0.5v v fb = 0.7v, mode = 0v run = 0v 26 0.1 500 35 1 a a a f osc oscillator frequency v fb = 0.6v 1.8 2.25 2.7 mhz f sync synchronous frequency v fb = 0.6v 1 3 mhz i lim peak switch current v in = 3v, v fb = 0.5v, duty cycle < 35% 650 1000 ma r ds(on) p-channel on resistance (note 6) n-channel on resistance (note 6) i sw = 100ma i sw = C100ma 0.5 0.35 0.65 0.55 electrical characteristics absolute axi u rati gs w ww u top view run sw v fb v in gnd dc package 6-lead (2mm 2mm) plastic dfn 4 5 7 6 3 2 1 mode / sync t jmax = 125c, ja = 40c/w, jc = 3c/w (soldered to a 4-layer board, note 3) exposed pad (pin 7) is pgnd, must be soldered to pcb v in 1 gnd 2 v fb 3 6 sw 5 mode/sync 4 run top view s6 package 6-lead plastic tsot-23 t jmax = 125c, ja = 250c/w order part number dc part marking order part number s6 part marking ltc3542edc lcfr ltc3542es6 lcfs order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. junction temperature (note 7) ............................. 125c storage temperature range ................... C65c to 125c lead temperature (soldering, 10 sec) tsot-23 ............................................................ 300c re? ow peak body temperature (dfn) .................. 260c package/order i for atio uu w
ltc3542 3 3542f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. no pin should exceed 6v. note 2: the ltc3542 is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: failure to solder the exposed pad of the package to the pc board will result in a thermal resistance much higher than 40c/w. symbol parameter conditions min typ max units i sw(lkg) switch leakage current v in = 5v, v run = 0v, v sw = 0v or 5v 0.01 1 a v uvlo undervoltage lockout threshold v in rising v in falling 1.8 2.0 1.9 2.3 v v v run run threshold 0.3 1.5 v i run run leakage current 0.01 1 a v mode/sync mode/sync threshold 0.3 1.2 v i mode/sync mode/sync leakage current 0.01 1 a the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.6v unless otherwise noted. electrical characteristics note 4: the converter is tested in a proprietary test mode that connects the output of the error ampli? er to the sw pin, which is connected to an external servo loop. note 5: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 6: the dfn switch on resistance is guaranteed by correlation to wafer level measurements. note 7: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ) ? ( ja ). burst mode operation pulse skip mode operation start-up from shutdown typical perfor a ce characteristics uw sw 2v/div v in = 3.6v v out = 1.8v i load = 25ma figure 3a circuit 2 s/div 3542 g01 v out 50mv/div ac coupled i l 100ma/div sw 2v/div i l 100ma/div v in = 3.6v v out = 1.8v i load = 25ma figure 3a circuit 400ns/div 3542 g02 v out 50mv/div ac coupled run 2v/div i l 100ma/div v in = 3.6v v out = 1.8v i load = 0a figure 3a circuit 400 s/div 3542 g03 v out 1v/div t a = 25c unless otherwise speci? ed.
ltc3542 4 3542f start-up from shutdown load step reference voltage vs temperature oscillator frequency vs temperature oscillator frequency vs supply voltage output voltage vs supply voltage output voltage vs load current r ds(on) vs input voltage run 2v/div i l 500ma/div v in = 3.6v v out = 1.8v i load = 500ma figure 3a circuit 400 s/div 3542 g04 v out 1v/div v out 100mv/div ac coupled i l 500ma/div v in = 3.6v v out = 1.8v i load = 30ma to 500ma figure 3a circuit 20 s/div 3542 g05 i load 500ma/div load step v out 100mv/div ac coupled i l 500ma/div v in = 3.6v v out = 1.8v i load = 0ma to 500ma figure 3a circuit 20 s/div 3542 g06 i load 500ma/div temperature ( c) C50 v ref (v) 0.6100 0.6075 0.6050 0.6025 0.6000 0.5975 0.5950 0.5925 0.5900 0.5875 0.5850 0.5825 0.6125 0.6150 0 50 75 3542 g07 C25 25 100 125 input voltage (v) 2 C0.5 v out error (%) C0.4 C0.2 C0.1 0 0.5 0.2 3 4 4.5 3542 g10 C0.3 0.3 0.4 0.1 2.5 3.5 5 5.5 6 v out = 1.8v i out = 100ma load current (ma) 1 0 v out error (%) 1.0 2.0 10 100 1000 3542 g11 C1.0 C0.5 0.5 1.5 C1.5 C2.0 burst mode operation v in = 3.6v v out = 1.8v pulse skip mode v in (v) 1 0 r ds(on) ( ) 0.1 0.3 0.4 0.5 5 0.9 3542 g12 0.2 3 26 47 0.6 0.7 0.8 synchronous switch main switch typical perfor a ce characteristics uw t a = 25c unless otherwise speci? ed. temperature ( c) C50 C30 C10 10 30 50 70 90 110 1.8 frequency (mhz) 1.9 2.1 2.2 2.3 2.7 3542 g08 2.0 2.4 2.5 2.6 supply voltage (v) frequency (mhz) 2.2 2.3 2.4 56 3542 g09 2.1 2.0 1.8 2 3 4 1.9 2.7 2.5 2.6
ltc3542 5 3542f r ds(on) vs temperature switch leakage vs input voltage ef? ciency vs input voltage temperature ( c) C50 0 r ds(on) ( ? ) 0.1 0.3 0.4 0.5 50 0.9 3542 g13 0.2 0 C25 75 100 25 125 0.6 0.7 0.8 v in = 2.7v v in = 3.6v v in = 4.2v synchronous switch main switch switch leakage vs temperature temperature ( c) C50 switch leakage (na) 200 250 300 25 75 3542 g15 150 100 C25 0 50 100 125 50 0 main switch synchronous switch v in (v) 0 0 leakage current (pa) 200 400 600 1 2 34 3542 g14 5 800 1000 100 300 500 700 900 6 synchronous switch main switch input voltage (v) 2.5 100 90 80 70 60 50 40 30 45 3542 g16 3 3.5 4.5 5.5 efficiency (%) i out = 500ma i out = 100ma i out = 10ma i out = 1ma i out = 0.1ma v out = 1.8v burst mode operation figure 3a circuit ef? ciency vs load current output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3542 g17 0 1 v in = 2.7v v in = 3.6v v in = 4.2v v out = 1.8v burst mode operation figure 3a circuit ef? ciency vs load current ef? ciency vs load current output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3542 g18 0 1 v in = 2.7v v in = 3.6v v in = 4.2v v out = 1.2v burst mode operation figure 3a circuit output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3542 g19 0 1 burst mode operation v in = 3.6v v out = 1.8v figure 3a circuit pulse skip mode typical perfor a ce characteristics uw t a = 25c unless otherwise speci? ed.
ltc3542 6 3542f block diagra w C + + C + C + C + 0.6v ea v b v fb v in sw mode/sync run v in shutdown burst mode clkin i comp slope compensation anti- shoot through mode detect 0.6v ref osc gnd 3542 bd i rcmp logic uu u pi fu ctio s v fb (pin 1/pin 3): output feedback pin. receives the feedback voltage from an external resistive divider across the output. nominal voltage for this pin is 0.6v. v in (pin 2/pin 1): power supply pin. must be closely decoupled to gnd. gnd (pin 3/pin 2): ground pin. sw (pin 4/pin 6): switch node connection to inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. mode/sync (pin 5/pin 5): mode selection and oscillator synchronization pin. this pin controls the operation of the device. when tied to gnd or v in , burst mode operation or pulse skipping mode is selected, respectively. do not ? oat this pin. the oscillation frequency can be synchronized to an external oscillator applied to this pin and pulse skipping mode is automatically selected. run (pin 6/pin 4): converter enable pin. forcing this pin above 1.5v enables this part, while forcing it below 0.3v causes the device to shut down. in shutdown, all functions are disabled drawing <1a supply current. this pin must be driven; do not ? oat. gnd (pin 7, dfn package only): exposed pad. the ex- posed pad is ground. it must be soldered to pcb ground to provide both electrical contact and optimum thermal performance. (dfn/tsot-23)
ltc3542 7 3542f operatio u the ltc3542 uses a constant frequency, current mode, step-down architecture. the operating frequency is set at 2.25mhz and can be synchronized to an external oscillator. to suit a variety of applications, the selectable mode/sync pin allows the user to trade-off noise for ef? ciency. the output voltage is set by an external divider returned to the v fb pin. an error ampli? er compares the divided output voltage with a reference voltage of 0.6v and adjusts the peak inductor current accordingly. main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle when the v fb voltage is below the reference voltage. the current ? ows into the inductor and the load increases until the current limit is reached. the switch turns off and energy stored in the inductor ? ows through the bottom switch (n-channel mosfet) into the load until the next clock cycle. the peak inductor current is controlled by the internally compensated output of the error ampli? er. when the load current increases, the v fb voltage decreases slightly below the reference. this decrease causes the error ampli? er to increase its output voltage until the average inductor cur- rent matches the new load current. the main control loop is shut down by pulling the run pin to ground. low load current operation by selecting mode/sync pin, two modes are available to control the operation of the ltc3542 at low load currents. both modes automatically switch from continuous opera- tion to the selected mode when the load current is low. to optimize ef? ciency, the burst mode operation can be selected. when the converter is in burst mode operation, the peak current of the inductor is set to approximately 60ma regardless of the output load. each burst event can last from a few cycles at light loads to almost continuously cycling with short sleep intervals at moderate loads. in between these burst events, the power mosfets and any unneeded circuitry are turned off, reducing the quiescent current to 26a. in this sleep state, the load current is being supplied solely from the output capacitor. as the output voltage drops, the ea ampli? ers output rises above the sleep threshold and turns the top mosfet on. this process repeats at a rate that is dependent on the load demand. by running cycles periodically, the switching losses which are dominated by the gate charge losses of the power mosfets are minimized. for lower ripple noise at low load currents, the pulse skip mode can be used. in this mode, the regulator continues to switch at a constant frequency down to very low load currents, where it will begin skipping pulses. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases to 100%, which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. an important design consideration is that the r ds(on) of the p-channel switch increases with decreasing input supply voltage (see typical performance characteristics). therefore, the user should calculate the power dissipation when the ltc3542 is used at 100% duty cycle with low input voltage (see thermal considerations in the applications information section). low supply operation to prevent unstable operation, the ltc3542 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2v. internal soft-start at start-up when the run pin is brought high, the internal reference is linearly ramped from 0v to 0.6v in about 1ms. the regulated feedback voltage follows this ramp resulting in the output voltage ramping from 0% to 100% in 1ms. the current in the inductor during soft-start is de? ned by the combination of the current needed to charge the output capacitance and the current provided to the load as the output voltage ramps up. the start-up waveform, shown in the typical performance characteristics, shows the output voltage start-up from 0v to 1.8v with a 500ma load and v in = 3.6v (refer to figure 3a).
ltc3542 8 3542f applicatio s i for atio wu uu a general ltc3542 application circuit is shown in figure1. external component selection is driven by the load require- ment and begins with the selection of the inductor l. once the inductor is chosen, c in and c out can be selected. the burst clamp. lower inductor values result in higher ripple current which causes the transition to occur at lower load currents. this causes a dip in ef? ciency in the upper range of low current operation. in burst mode operation, lower inductance values cause the burst frequency to increase. inductor core selection different core materials and shapes change the size/current and price/current relationships of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs size requirements and any radiated ? eld/emi requirements than on what the ltc3542 requires to operate. table 1 shows some typi- cal surface mount inductors that work well in ltc3542 applications. input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out /v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ii vvv v rms max out in out in () C where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur- rent, i max = i lim C i l /2. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case is commonly used to design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours life time. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the v in ltc3542 run r1 3542 f01 r2 c f l c in c out sw v in 2.7v to 5.5v v out v fb mode/sync gnd figure 1. ltc3542 general schematic inductor selection the inductor value has a direct effect on ripple current i l , which decreases with higher inductance and increases with higher v in or v out , as shown in following equation: ? i v l v v l out o out in = ? ? ? ? ? ? ? ? C 1 where f o is the switching frequency. a reasonable starting point for setting ripple current is i l = 0.4 ? i out(max) , where i out(max) is 500ma. the largest ripple current i l occurs at the maximum input voltage. to guarantee that the ripple current stays below a speci? ed maximum, the inductor value should be chosen according to the follow- ing equation: l v i v v out ol out in max = ? ? ? ? ? ? ? ? C () ? 1 the dc current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. thus, a 600ma rated inductor should be enough for most applications (500ma + 100ma). for better ef? ciency, chose a low dc-resistance inductor. the inductor value will also have an effect on burst mode operation. the transition to low current operation begins when the inductors peak current falls below a level set by
ltc3542 9 3542f design. an additional 0.1f to 1f ceramic capacitor is also recommended on v in for high frequency decoupling, when not using an all ceramic capacitor solution. output capacitor (c out ) selection the selection of c out is driven by the required esr to minimize voltage ripple and load step transients. typically, once the esr requirement is satis? ed, the rms current rating generally far exceeds the i ripple(p-p) requirement, except for an all ceramic solution. the output ripple ( v out ) is determined by: ?? v i esr c out l out + ? ? ? ? ? ? 1 8? ? ? o where f o is the switching frequency, c out is the output capacitance and i l is the inductor ripple current. for a ? xed output voltage, the output ripple is highest at maximum input voltage since i l increases with input voltage. if tantalum capacitors are used, it is critical that the capaci- tors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. these are specially constructed and tested for low esr so they give the lowest esr for a given volume. other capacitor types include sanyo poscap, kemet t510 and t495 series, and sprague 593d and 595d series. consult the manufacturer for other speci? c recommendations. ceramic input and output capacitors higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current rating, high voltage rating and low esr are tempting for switching regulator use. however, the esr is so low that it can cause loop stability problems. since the ltc3542s control loop does not depend on the output capacitors esr for stable operation, ceramic capacitors can be used to achieve very low output ripple and small circuit size. x5r or x7r ceramic capacitors are recommended because these dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. great care must be taken when using only ceramic input and output capacitors. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. for more information, see application note 88. the recommended capacitance value to use is 10f for both input and output capacitors. applicatio s i for atio wu uu table 1. representative surface mount inductors manufacturer part number value (h) max dc current (a) dcr ( ) size (mm 3 ) sumida cdrh2d11-2rm 2.2 0.780 0.098 3.2 3.2 1.2 cdrh3d16 2.2 1.2 0.075 3.8 3.8 1.8 cmd4d11 2.2 0.95 0.116 4.4 5.8 1.2 cdh2d09b 3.3 0.85 0.15 2.8 3 1 cls4d09 4.7 0.75 0.15 4.9 4.9 1 murata lqh32cn 2.2 0.79 0.097 2.5 3.2 1.55 lqh43cn 4.7 0.75 0.15 4.5 3.2 2.6 tdk ivlc453232 2.2 0.85 0.18 4.8 3.4 3.4 vlf3010at- 2r2m1r0 2.2 1.0 0.12 2.8 2.6 1
ltc3542 10 3542f output voltage programming the output voltage is set by a resistive divider according to the following formula: vv r r out =+ ? ? ? ? ? ? 06 1 2 1 . to improve the frequency response, a feed-forward capaci- tor, c f , may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. mode selection and frequency synchronization the mode/sync pin is a multipurpose pin that provides mode selection and frequency synchronization. connect- ing this pin to gnd enables burst mode operation, which provides the best low current ef? ciency at the cost of a higher output voltage ripple. connecting this pin to v in selects pulse skip mode operation, which provides the lowest output ripple at the cost of low current ef? ciency. the ltc3542 can also be synchronized to an external clock signal with range from 1mhz to 3mhz by the mode/sync pin. during synchronization, the mode is set to pulse skip and the top switch turn-on is synchronized to the falling edge of the external clock. ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. ef? ciency can be expressed as: ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in ltc3542 circuits: 1) v in quiescent current, 2) i 2 r loss and 3) switching loss. v in quiescent current loss dominates the power loss at very low load currents, whereas the other two dominate at medium to high load currents. in a typical ef? ciency plot, the ef? ciency curve at very low load currents can be misleading since the actual power loss is of no consequence as illustrated in figure 2. 1) the v in quiescent current is the dc supply current given in the electrical characteristics which excludes mosfet charging current. v in current results in a small (<0.1%) loss that increases with v in , even at no load. 2) i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current ? ows through inductor l, but is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (d) as follows: r sw = (r ds(on)top )(d) + (r ds(on)bot )(1 C d) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) applicatio s i for atio wu uu figure 2. power loss vs load current output current (ma) 1 power loss (mw) 10 100 1000 0.1 10 100 1000 3542 f02 0.1 1 v out = 2.5v v out = 1.8v v out = 1.2v v in = 3.6v burst mode operation
ltc3542 11 3542f 3) the switching current is mosfet gate charging current, that results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continuous mode, i gatechg = f o (q t + q b ), where q t and q b are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. other hidden losses such as copper trace and internal battery resistances can account for additional ef? ciency degradations in portable systems. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. other losses include diode conduction losses during dead-time and inductor core losses generally account for less than 2% total ad- ditional loss. thermal considerations in most applications the ltc3542 does not dissipate much heat due to its high ef? ciency. but in applications where the ltc3542 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3542 from exceeding the maximum junction temperature, the user need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t r = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient. applicatio s i for atio wu uu the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. as an example, consider the ltc3542 in dropout at an input voltage of 2.7v, a load current of 500ma and an ambient temperature of 70c. from the typical performance graph of switch resistance, the r ds(on) of the p-channel switch at 70c is approximately 0.7 . therefore, power dissipated by the part is: p d = i load 2 ? r ds(on) = 175mw for the dfn package, the ja is 40c/w. thus, the junction temperature of the regulator is: t j = 70c + 0.175 ? 40 = 77c which is below the maximum junction temperature of 125c. note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (r ds(on) ). checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or dis- charge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a re- view of control loop theory, refer to application note 76. in some applications, a more severe transient can be caused by switching loads with large (>1f) bypass capacitors. the discharged bypass capacitors are effectively put in
ltc3542 12 3542f parallel with c out , causing a rapid drop in v out . no regula- tor can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap tm controller is designed speci? cally for this purpose and usually incorporates cur- rent limit, short circuit protection and soft-start. design example as a design example, assume the ltc3542 is used in a single lithium-ion battery-powered cellular phone application. the v in will be operating from a maximum of 4.2v down to about 2.7v. the load current requirement is a maximum of 0.5a, but most of the time it will be in standby mode, requiring only 2ma. ef? ciency at both low and high load currents is important. output voltage is 1.8v. with this information we can calculate l using: l fi v v v l out out in = ? ? ? ? ? ? 1 1 ? ??C ? substituting v out = 1.8v, v in = 4.2v, i l = 200ma and f = 2.25mhz gives: l v mhz ma v v h = ? ? ? ? ? ? = 18 2 25 200 1 18 42 228 . .? ?C . . . choosing a vendors closest inductor value of 2.2h results in a maximum ripple current of: ? i v mhz h v v l = ? ? ? ? ? ? = 18 225 22 1 18 42 207 . .?. ?C . . .8 8ma applicatio s i for atio wu uu hot swap is a trademark of linear technology corporation. c in will require an rms current rating of at least 0.25a ? i load(max) /2 at temperature and c out will require esr of less than 0.2 . in most cases, ceramic capacitors will satisfy these requirements. select c out = 10f and c in = 10f. for the feedback resistors, choose r1 = 75k, r2 can be calculated from: r v v r v v k out 2 06 11 18 06 175 = ? ? ? ? ? ? = ? ? ? ? ? ? . C? . . C? == 150k figure 3 shows the complete circuit along with its ef? ciency curve, load step response and recommended layout pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3542. these items are also illustrated graphically in figure 3b. check the following in your layout: 1. the power traces, consisting of the gnd trace, the sw trace and the v in trace should be kept short, direct and wide. 2. does the v fb pin connect directly to the feedback re- sistors? the resistive divider r1/r2 must be connected between the (+) plate of c out and ground. 3. does the (+) plate of c in connect to v in as closely as possible? this capacitor provides the ac current to the internal power mosfets. 4. keep the (C) plates of c in and c out as close as pos- sible. 5. keep the switching node, sw, away from the sensitive v fb node.
ltc3542 13 3542f applicatio s i for atio wu uu figure 3a. typical application figure 3b. layout diagram figure 3c. ef? ciency curve figure 3d. load step v in ltc3542 run r1 75k *sumida cdrh2d18hd-2r2nc **tdk c2012x5r0j106m 3542 f03a r2 150k c f 22pf l* 2.2 h c in ** 10 f c out ** 10 f sw v in 2.7v to 5.5v v out 1.8v 500ma v fb mode/sync gnd 1 2 3 v fb r1 v in v in gnd 3542 f03b c in 6 5 gnd 4 run gnd gnd via to v out mode/ sync sw r2 c f c out l v out output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3542 g17 0 1 v in = 2.7v v in = 3.6v v in = 4.2v v out = 1.8v burst mode operation figure 3a circuit v out 100mv/div ac coupled i l 500ma/div v in = 3.6v v out = 1.8v i load = 0ma to 500ma figure 3a circuit 20 s/div 3542 g06 i load 500ma/div
ltc3542 14 3542f u package descriptio dc package 6-lead plastic dfn (2mm 2mm) (reference ltc dwg # 05-08-1703) 2.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (wccd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.05 bottom viewexposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ 1.37 0.05 (2 sides) 1 3 6 4 pin 1 bar top mark (see note 6) 0.200 ref 0.00 C 0.05 (dc6) dfn 1103 0.25 0.05 0.50 bsc 0.25 0.05 1.42 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.675 0.05 2.50 0.05 package outline 0.50 bsc pin 1 chamfer of exposed pad
ltc3542 15 3542f u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 6 plcs (note 3) datum a 0.09 C 0.20 (note 3) s6 tsot-23 0302 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
ltc3542 16 3542f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0906 ? printed in usa part number description comments ltc3405/ltc3405b 300ma i out , 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 20a, i sd < 1a, thinsot package ltc3406/ltc3406b 600ma i out , 1.5mhz, synchronous step-down dc/dc converter 96% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, i sd < 1a, thinsot package ltc3407/ltc3407-2 dual 600ma/800ma i out , 1.5mhz/2.25mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, ms10e, dfn packages ltc3409 600ma i out , 1.7mhz/2.6mhz, synchronous step-down dc/dc converter 96% ef? ciency, v in : 1.6v to 5.5v, v out(min) = 0.6v, i q = 65a, i sd < 1a, dfn package ltc3410/ltc3410b 300ma i out , 2.25mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 26a, i sd < 1a, sc70 package ltc3411 1.25a i out , 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd < 1a, ms10, dfn packages ltc3548 dual 400ma/800ma i out , 2.25mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, ms10, dfn packages ltc3561 1a i out , 4mhz synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.6v to 5.5v, v out(min) = 0.8v, i q = 240a, i sd < 1a, 3mm 3mm dfn package related parts u typical applicatio using low pro? le components, <1mm height v in ltc3542 run 75k *tdk vlf3010at-2r2mir0 **tdk c2012x5r0j106m 3542 ta02a 150k 22pf 2.2 h* c in ** 10 f cer c out ** 10 f cer sw 2 6 4 1 3 5 v in 2.7v to 5.5v v out 1.5v 500ma v fb mode/sync gnd ef? ciency vs output current output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3542 ta02b 0 1 v in = 3.6v v out = 1.5v burst mode operation

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